The present invention generally relates to a semiconductor integrated circuit device incorporating a MIS (Metal Insulator Semiconductor) transistor. More particularly, the present invention relates to a measure to reduce electromagnetic radiation intensity.
Conventionally, it is known that electronic equipments generate unwanted electromagnetic radiation called EMI (Electromagnetic Interference) radiation. It is desired that this EMI radiation be as small as possible due to its possible interference with operation of another electronic equipment. Therefore, the EMI radiation intensity is subjected even to the legal controls. The EMI radiation is generated due to various causes, but operating characteristics of a huge number of transistors included in LSI (Large Scale Integration) of the electronic equipment, particularly MOS (Metal Oxide Semiconductor) transistors in a CMOS (Complementary Metal-Oxide Semiconductor) integrated circuit, are an important cause. A switching waveform of the MOS transistor includes high-frequency components due to an abrupt change in voltage and current. Accordingly, a portion serving an antenna within the electronic equipment generates unwanted electromagnetic radiation according to such an abrupt change.
In the frequency range up to several tens of gigahertz (GHz), a semiconductor integrated circuit device itself has low EMI radiation intensity because it has few portions serving as an antenna. However, when a semiconductor chip, i.e., a semiconductor integrated circuit device, is mounted on a printed circuit board or a package, power supply lines and signal lines having several to several tens of centimeters are extended therein. Thus, these power supply lines and signal lines serve as an antenna, increasing the EMI radiation intensity. Moreover, the EMI radiation intensity largely depends on a mounting form. It is preferable to avoid a mounting form that has a large number of portions serving an antenna as much as possible. In general, in order to reduce the EMI radiation intensity, a pattern shape of the power supply and signal lines on the printed circuit board is changed, or a part having a function to suppress a high-frequency current such as ferrite beads is incorporated. However, these methods are often based on the empirical rule. Therefore, prediction of the effect is difficult, and the costs are also increased. Accordingly, it is preferable to reduce the EMI radiation at the MOS transistor level in the semiconductor integrated circuit device, thereby ensuring the flexibility of mounting forms without considering the EMI radiation.
In particular, the MOS transistors in the recent CMOS semiconductor integrated circuit devices have an increased operation speed as a result of the progress in miniaturization technology. This causes ever-increasing EMI radiation intensity due to an increased switching operation speed, i.e., rise and fall time, of the MOS transistors. In this respect as well, means for effectively reducing the EMI radiation in connection with the operating characteristics of the MOS transistors has been greatly demanded.
The following methods have been proposed for reducing the EMI radiation in connection with the operation characteristics of the MOS transistors in the semiconductor integrated circuit device:
(1) Optimize the transistor size. More specifically, the rising/falling rate of a voltage waveform (which is referred to as xe2x80x9cslew ratexe2x80x9d) is reduced as much as possible in order to reduce harmonic components of the frequency included in a voltage amplitude. Alternatively, the slew rate and maximum amplitude of a current waveform in the switching operation of the transistors are reduced in order to suppress the intensity of electromagnetic waves generated from a power supply line and the like;
(2) Avoid simultaneous switching of the transistors. More specifically, the delay time is adjusted so as to disperse the switching time of the transistors, thereby reducing concentrated generation of electromagnetic waves (EMI radiation) from a power supply line due to simultaneous switching. Thus, the EMI radiation intensity from the power supply line and the like is reduced; and
(3) Using a spread spectrum clock system, i.e., technology of reducing the EMI radiation by frequency modulation of a clock signal, to suppress the intensity of electromagnetic waves generated from the clock system.
The spread spectrum clock system is the technology of varying a clock frequency (fc) by a small amount (xcex4) in a period of a modulation frequency (fm), and thus diffusing the energy distribution of harmonic EMI radiation of the clock in a high-frequency region, thereby reducing the peak value of the EMI radiation. This technology is widely used in the recent CMOS semiconductor integrated circuit devices, and is described in, e.g., U.S. Pat. No. 5,488,627 titled xe2x80x9cSpread Spectrum Clock Generator and Associated Methodxe2x80x9d. For example, the use of the spread spectrum clock system enables reduction in electric field intensity of the EMI radiation by about 10 dB by, e.g., setting the modulation frequency (fm) to 50 KHz, i.e., about 0.5% of the clock frequency (fc) of the frequency shift (xcex4). It is known that the harmonic intensity distribution of the clock in the high-frequency region has a width of about xcex4, and the profile thereof is determined by time variation of xcex4 in a period of 1/fm (which is referred to as modulation profile). In general, clock-related circuitry includes a clock generation circuit for generating a clock signal, and a clock buffer for distributing the generated clock to each circuit within the integrated circuit. In the spread spectrum clock system, a frequency-modulated clock is generated by the clock generation circuit, and then supplied from the clock buffer to each circuit.
It is an object of the present invention to implement a semiconductor integrated circuit device generating reduced EMI radiation while operating at a high speed, by finely dispersing the rise and fall of each MOS transistor by using relatively simple design and structure in view of operating characteristics of the MOS transistors in the semiconductor integrated circuit device.
According to the present invention, a semiconductor integrated circuit device integrating a plurality of MIS (Metal Insulator Semiconductor) transistors each having its source and drain provided in a respective region of a semiconductor substrate that is surrounded by a substrate region, and its gate provided on a region of the semiconductor substrate that is located between the source and drain, wherein the plurality of MIS transistors include at least one of a P-channel modulation MIS transistor and an N-channel modulation MIS transistor, a modulation substrate bias Vb varying with a prescribed amplitude within such a range that causes no latch-up is applied to the P-channel modulation MIS transistor, and a modulation substrate bias Vbxe2x80x2 varying with a prescribed amplitude within such a range that causes no latch-up is applied to the N-channel modulation MIS transistor.
Thus, in response to application of the modulation substrate bias to the substrate region of the modulation MIS transistor, a threshold voltage and current driving capability of the modulation MIS transistor vary with time within the range that causes no latch-up. Accordingly, a logic threshold voltage, delay time, and rise and fall time of an output waveform of, e.g., a complementary logic gate including the modulation MOS transistor are modulated, whereby energy spectrum of electromagnetic waves radiated during signal transition has a larger peak width than that in the case where there is no modulation. Accordingly, the peak value and thus the EMI radiation intensity are reduced while maintaining a proper operation of the semiconductor integrated circuit device.
Preferably, in the aforementioned semiconductor integrated circuit device, the modulation substrate bias Vb varying with the prescribed amplitude within a range of Vbxe2x89xa7Vddxe2x88x92Vf is applied to a substrate region of the P-channel modulation MIS transistor, where Vdd is a drain potential, Vss is a source potential, and Vf is a forward voltage across a PN junction between the drain and the substrate region, and the modulation substrate bias Vbxe2x80x2 varying with the prescribed amplitude within a range of Vbxe2x80x2xe2x89xa6Vss+Vfxe2x80x2 is applied to a substrate region of the N-channel modulation MIS transistor, where Vdd is a drain potential, Vss is a source potential, and Vfxe2x80x2 is a forward voltage across a PN junction between the substrate region and the source. Thus, even in the structure of a complementary MIS transistor, a forward voltage that activates a parasitic bipolar transistor is not applied. As a result, malfunction such as latch-up due to actuation of a parasitic bipolar transistor is more reliably prevented.
Preferably, the semiconductor integrated circuit device further includes a driving circuit for driving a gate electrode of the MIS transistors through which a current having an at least predetermined change rate and at least predetermined variation flows between the drain and source electrodes thereof during switching operation, and the driving circuit includes the modulation MIS transistor. Thus, a modulated output of the driving circuit is applied to the gate electrode of a MIS transistor having a particularly large variation in current. Therefore, the switching (ON/OFF switching) timing of this MIS transistor is modulated, whereby energy distribution of electromagnetic waves resulting from signal transition has a wider, gentler peak, whereby the EMI radiation can be effectively reduced. By forming a limited number of MIS transistors from a modulation MIS transistor, the number of extended electrodes of a substrate bias provided separately from the extended electrodes of the source and drain is suppressed. As a result, increase in layout area can be suppressed.
Preferably, the semiconductor integrated circuit device includes at least two circuits each including a plurality of MIS transistors including the modulation MIS transistor, and having different overall delay times, and a modulation substrate bias having a larger amplitude is applied to the circuit having a shorter delay time than to the circuit having a longer delay time. Thus, EMI radiation can be effectively reduced within the range that causes no defective signal transmission in the entire semiconductor integrated circuit device.
Preferably, the semiconductor integrated circuit device further includes a modulation substrate bias generation circuit having a function to program a waveform profile of the modulation substrate bias. Thus, various kinds of devices adaptable to various mounting forms can be implemented with a single device, i.e., with the same structure, and also a semiconductor integrated circuit device having an optimized balance between the EMI radiation and the operation speed can be obtained.
Preferably, the semiconductor integrated circuit device includes: a memory cell array having a plurality of memory cells arranged therein; bit line pairs connected to the memory cell array; precharge transistors for precharging the bit line pairs; and a driving circuit for driving gate electrodes of the precharge transistors, wherein at least one of the driving circuit and the precharge transistors includes the modulation MIS transistor. Thus, a current flowing through the precharge transistors during precharge operation of the bit lines can be subjected to frequency modulation. Normally, the EMI radiation is rapidly increased when a multiplicity of bit lines are precharged. However, the peak of the EMI radiation can be reduced by application of a modulated current.
Preferably, the semiconductor integrated circuit device includes: a circuit including a plurality of MIS transistors, the plurality of MIS transistors being part of the plurality of MIS transistors; a bus signal line extended from the circuit; and a driving circuit provided in the circuit, for outputting data to the bus signal line, the driving circuit including the modulation MIS transistor. Thus, a power supply current and output waveform of the driving circuit are subjected to frequency modulation. Normally, the EMI radiation is rapidly increased when the bus has a multi-bit width. According to the present invention, however, such frequency modulation enables reduction in the peak value of the EMI radiation.
Preferably, the semiconductor integrated circuit device includes a driving circuit of a pad for receiving and outputting a signal from and to an external equipment of the semiconductor integrated circuit device, the driving circuit of the pad including the modulation MIS transistor. Thus, the slew rate of an output waveform of the pad is subjected to frequency modulation, whereby the peak of the EMI radiation is reduced. Moreover, a power supply current is modulated. Although EMI radiation from a power supply line is significantly increased due to simultaneous signal transition of the driving circuits of the pads, the peak of such EMI radiation can also be reduced by such a modulated power supply current. The transistor in the driving circuit of the pad generally has a high EMI radiation level since it receives a large current and is directly connected to an external wiring serving as an antenna. According to the present invention, however, such EMI radiation can also be effectively reduced.
According to the present invention, an electronic equipment has mounted therein a plurality of first semiconductor integrated circuit devices and a second semiconductor integrated circuit, wherein each of the first semiconductor integrated circuit devices is a semiconductor integrated circuit device integrating a plurality of MIS transistors each having its source and drain provided in a respective region of a semiconductor substrate that is surrounded by a substrate region, and its gate provided on a region of the semiconductor substrate that is located between the source and drain, the plurality of MIS transistors include at least one of a P-channel modulation MIS transistor and an N-channel modulation MIS transistor, a modulation substrate bias Vb varying with a prescribed amplitude within such a range that causes no latch-up is applied to the P-channel modulation MIS transistor, and a modulation substrate bias Vbxe2x80x2 varying with a prescribed amplitude within such a range that causes no latch-up is applied to the N-channel modulation MIS transistor, and the second semiconductor integrated circuit device includes a modulation substrate bias generation circuit for generating the modulation substrate bias to be supplied to each of the first semiconductor integrated circuit devices.
This eliminates the need to provide a substrate bias generation circuit in each semiconductor integrated circuit device, enabling reduction in costs.
Preferably, in the first semiconductor integrated circuit devices, the modulation substrate bias Vb varying with the prescribed amplitude within a range of Vb.Vddxe2x88x92Vf is applied to a substrate region of the P-channel modulation MIS transistor, where Vdd is a drain potential, Vss is a source potential, and Vf is a forward voltage across a PN junction between the drain and the substrate region, and the modulation substrate bias Vbxe2x80x2 varying with the prescribed amplitude within a range of Vbxe2x80x2.Vss+Vfxe2x80x2 is applied to a substrate region of the N-channel modulation MIS transistor, where Vdd is a drain potential, Vss is a source potential, and Vfxe2x80x2 is a forward voltage across a PN junction between the substrate region and the source. Thus, latch-up can be reliably prevented even in a CMOS semiconductor integrated circuit device.